The present disclosure relates to the field of liquid crystal display, and more particularly, to a scanning driving circuit and a liquid crystal display panel with the scanning driving circuit.
The present disclosure relates to the gate driver on array (GOA) technique. The GOA technique is that a gate scanning driver signal circuit is produced on an array substrate using the thin-film transistor (TFT) liquid crystal display (LCD) array substrate manufacturing process to realize row-by-row scanning on gates.
Low temperature poly-silicon (LTPS) semiconductor TFTs gradually develop. Also, the LTPS semiconductor has a feature of extremely high carrier mobility. With these reasons, integrated circuit (IC) related to panels becomes one of the key focuses in the industry, which further attracts many people to commit themselves to studying system on panels (SOPs) for realization.
As FIG. 1 shows, the design of the GOA circuit in the related art adopts a driving method of interlace. Unilateral GOA circuit needs two CK signal lines, a STV routing, a reset routing, a VGH routing, a VGL routing, a U2D routing, and a D2U routing. The CMOS GOA circuit is defined by a signal input control module 100, a reset module 200, a latch module 300, a node signal processing module 400, and a buffer processing module 500. The signal input control module 100 is configured to control the input of signals of the GOA circuit, control a clock control inverter through a CK signal, and realize transmittance of signals on a previous stage Q node to further hold the Q node. The reset module 200 is configured to reset the node of the signal in the circuit. The latch module 300 is configured to hold the signal on the Q node. The node signal processing module 400 is configured to generate a gate driver signal through an NAND operation of the CK signal and the signal on the Q node. The buffer processing module 500 is configured to enhance the driving capacity of the gate signal.
Therefore, the scanning driving circuit in the related art uses a clock control inverter and an inverter for the design of the latch unit and adopts a clock signal to input the latch signal and control pull-down. However, the clock signal loads much in this design so the clock signal is hardly applied to a high-resolution panel.
In sum, the driver scanning circuit in the related art is somewhat defective and needs being improved.